Slot 3

High-Performance and Low-Energy Design, Modeling and Use of the Memory Hierarchy
Erik Hagersten, Uppsala University, Sweden


The introduction of multi/many-core systems has increased the importance of the memory hierarchy to hardware designers and software engineers alike. Future designs are moving towards GB-sized caches. This not only increases the need to understand the memory hierarchy, but also requires new efficient and accurate ways of modeling it. This course will cover:


Erik Hagersten has moved between industry and academia seven times and is currently a chaired professor in Computer Architecture at Uppsala University in Sweden. Before moving to Sweden he was the chief architect for the high-end server division at Sun Microsystems. His resent startup Acumem AB developing performance analysis tools for the memory hierarchy and was acquired by Rogue Wave Inc. in 2010.

Erik’s research interests focus on ultra-fast performance modeling techniques as well as the software and hardware optimizations they enable. In addition, he has a hard time resisting “traditional” architecture research since it is so much fun. In his prior research, he introduced the Cache-Only Memory Architecture and its brain-dead acronym COMA.

He is a member of the Swedish Royal Academy of Science and Engineering and is this year’s recipient of Uppsala University’s most prestigious research award (Björkénska). He is happy to be back as an ACACES teacher this year. Last time was a blast!

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