Slot 4

Computing with FPGA-based Accelerators
Jason Anderson, University of Toronto, Canada

Abstract

Field-programmable gate arrays (FPGAs) are programmable chips that can be configured by the end user to implement any digital circuit.  Mainstream commercial FPGAs are "reconfigurable", meaning that a given FPGA device can be configured as a given circuit, and then later that same FPGA device can be re-configured as an entirely different circuit.  This reconfigurable nature allows FPGAs to be used as programmable computing platforms, where they are used to implement accelerators that work together with standard processors to improve computational throughput and energy efficiency.  Until recently however, FPGA technology has been inaccessible to those with solely software skills – the use of FPGAs required hardware design knowledge.  Thus, broad uptake of FPGAs for computing applications has been impeded by ease-of-use issues.

High-level synthesis (HLS) raises the abstraction level for hardware design by allowing a software program to be automatically synthesized into a hardware circuit.  HLS aims to offer the flexibility and ease-of-use associated with software, along with the speed and energy advantages of customized hardware.  Both of the major FPGA vendors have been investing heavily in HLS in recent years, and there has been much research on the topic in academia as well.  State-of-the-art HLS is nearing the point where software engineers are able to design hardware, and the quality of the HLS hardware produced being comparable to human-crafted implementations.
  
In this course, we will first overview FPGA technology, tools and architecture with a view of their application in compute acceleration, particularly in the embedded context.  We will then survey recent cases wherein FPGAs have been successful in improving application speed and power vs. the use of CPUs and GPUs.  Through this, students will gain awareness of the sorts of software applications for which FPGAs may be useful.  Finally, we will describe how FPGAs can be used by software programmers using high-level synthesis (HLS), covering both academic and commercial HLS offerings.  We will describe the typical knobs that are available in HLS to tailor the generated hardware to meet speed and area constraints.

Bio

Jason Anderson (http://janders.eecg.toronto.edu) received the B.Sc. degree in computer engineering from the University of Manitoba, and the M.A.Sc. and Ph.D. degrees in electrical and computer engineering (ECE) from the University of Toronto.  He is an Associate Professor with the Department of ECE, University of Toronto and holds the Jeffrey Skoll Chair in Software Engineering.  From 1997-2008, he was with the FPGA implementation tools group at Xilinx, Inc., in San Jose, CA, and Toronto, ON.  Prof. Anderson has received six awards for excellence in undergraduate teaching, four best papers awards, holds 25 U.S. patents, and has authored over 60 papers in refereed journals and symposia.  His research interests include all aspects of computer-aided design (CAD), architecture and circuits for FPGAs.   He is spearheading the LegUp open-source high-level synthesis project (http://legup.eecg.toronto.edu), which has been downloaded by over 1200 users worldwide.


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