While the notion of self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing, we are seeing the emerging need for self-awareness in the context of complex many-core chips that must address the (often conflicting) challenges of variability, resiliency, energy, heat, cost, performance, security, etc. in the face of highly dynamic operational behaviors and environmental conditions. A holistic, cross-layer approach is required to address these challenges, particularly in the context of complex Systems-on-Chip (SoCs). In this context, this course is organized into four sections:
(1.) I begin with a review of self-awareness in nature and the motivation for implementing selfawareness in embedded systems. I present a taxonomy of self-awareness to describe properties and levels of self-awareness, as well as how they can be realized in cost-efficient hardware structures, and the challenges faced during the design of self-aware embedded systems.
(2.) I present CyberPhysical-Systems-on-Chip (CPSoC), an exemplar of self-aware SoCs that intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness. The CPSoC design paradigm enables self-awareness (i.e., the ability of the system to observe its own internal and external behaviors such that it is capable of making judicious decision) and (opportunistic) adaptation using the concept of cross-layer physical and virtual sensing and actuations applied across different layers of the hardware/software system stack. The closed loop control used for adaptation to dynamic variation commonly known as the observe-decide- act (ODA) loop is implemented using an adaptive, reflexive middleware layer.
(3.) I present the principles behind variation-aware system design. By using over-designed (large) margins, existing approaches hide the variability in behavior of underlying system components (e.g., device-to-device, wearout, and environmental variability). This makes designs expensive, fragile and vulnerable to even the smallest changes in the environment or component failures. I present an approach to tame and exploit variability through a strategy where system components -- led by proactive software -- routinely monitor, predict and adapt to the variability of manufactured systems. Unlike conventional system design where variability is hidden behind the conservative specifications of an over-designed hardware, I describe strategies that expose spatiotemporal variations in hardware to the highest layers of software.
(4.) I present cross-layer strategies to address variability-aware memory management for nanoscale computing systems. The memory subsystem is a main contributor to the overall power consumption of the system, and also often the largest subsystem and thus most vulnerable to the effects of variations. I illustrate techniques to opportunistically exploit the hardware variations in on-chip and off-chip memory at the system level through the deployment of variation-aware software stacks.
Nikil Dutt is a Chancellor's Professor of CS, Cognitive Sciences, and EECS at the University of California, Irvine. He received a PhD from the University of Illinois at Urbana-Champaign (1989). His research interests are in embedded systems, EDA, computer architecture and compilers, distributed systems, and brain-inspired architectures and computing. He has received numerous best paper awards and is coauthor of 7 books. Professor Dutt has served as EiC of ACM TODAES and AE for ACM TECS and IEEE TVLSI. He is on the steering, organizing, and program committees of several premier EDA and Embedded System Design conferences and workshops, and has also been on the advisory boards of ACM SIGBED, ACM SIGDA, ACM TECS and IEEE ESL. He is a Fellow of the ACM and IEEE, and recipient of the IFIP Silver Core Award.