During the last years, manycores have been adopted to overcome the power limitation that impedes obtaining higher performance. Manycore systems imply an efficient interconnect inside the chip. Although the different cores can run in isolation and are somehow detached one from the others, the interconnect is a single entity and therefore emerges as a shared resource in the whole chip, potentially leading to become the bottleneck of the system. This imposes serious design challenges in the face of performance, manufacturing defects, wearing out of components, or even in new usage models.
In this course, we will design on-chip interconnects starting from basic foundations. We will identify new requirements imposed by the new challenges emerging in this domain and will provide cutting-edge mechanisms to support the new usage models. Different key technologies will be introduced and analyzed such as:
(*) Effective routing algorithms implementations to support manufacturing defects
(*) Aggressive on-the-fly reconfiguration strategies to support dynamicity in the system
(*) Efficient support of coherence protocols via built-in collective communication primitives
(*) Congestion and HOL-avoidance in resource-constrained environments
The course contents will be reinforced with examples of a complete manycore system implemented and emulated on a multi-FPGA prototyping system.
José Flich got his PhD in 2001 in Computer Engineering. He is Full Professor at UPV where he leads the research activities related to NoCs. He published over 150 conference and journal papers, and has served in different conference program committees (ISCA, PACT, HPCA, NOCS, ICPP, IPDPS, HiPC, CAC, CASS, ICPADS, ISCC), as program chair (INA-OCMC, CAC) and track co-chair (EUROPAR). José Flich has collaborated with different Institutions (Ferrara, Naples, Catania, Jonkoping, USC) and companies (AMD, Intel, Sun). Current research activities focus routing, coherency protocols and congestion management within NoCs. He has co-invented different routing strategies, reconfiguration and congestion control mechanisms, some of them with high recognition (RECN and LBDR for on-chip networks). He is a member of the HiPEAC. He is coeditor of the book "Designing Network-on-Chip Architectures in the Nanoscale Era", and Coordinated the FP7 NaNoC project and leads the H2020 MANGO project (http://www.mango-project.eu).