Slot 1

Superscalar Architecture
Mikko Lipasti, University of Wisconsin-Madison, USA

Abstract

In the twenty years from 1985 to 2005, state-of-the-art desktop and server processors evolved from simple, five-stage scalar pipelines clocked at approximately 10MHz to massively complex designs that support nearly 200 simultaneous in-flight instructions executing in very deep pipelines running at over 3GHz. From 2002-2012, mobile processors traversed a similar evolutionary path, with today’s leading-edge mobile processors nearly matching their desktop counterparts in microarchitectural complexity and peak clock frequency, while operating within a minuscule power envelope of just 2-3W.

This course will detail the numerous microarchitectural advances that enabled these incredible improvements in performance, usability, and power efficiency. We will show how a modern processor must carefully match its rates of instruction flow, register data flow, and memory data flow in order to realize a balanced design without any single bottleneck that cripples overall performance. Advanced topics in front-end microarchitecture will include instruction fetch logic, the most recent advances in branch prediction, as well as instruction-side caching and prefetching. Advanced topics in register data flow will include register renaming, register file and bypass network design, and design of state-of-the-art execution pipeline. Finally, advanced topics in memory data flow will include load/store disambiguation and memory dependence prediction, advanced nonblocking cache design, sophisticated data prefetching schemes, and high-performance main memory technology.

Bio

Prof. Lipasti is an established expert in the design of high-performance, low-power, and reliable processor cores; networks-on-chip for many-core processors; and fundamentally new, biologically-inspired models of computation. He was named an IEEE Fellow (class of 2013) "for contributions to the microarchitecture and design of high-performance microprocessors and computer systems." He has published over 100 refereed papers, advised 17 Ph.D. theses to completion, and is a charter member of the ISCA, MICRO, and HPCA Halls of Fame. In 2012, he co-founded Thalchemy Corp, a startup company that is developing novel algorithms and accelerators to enable ultra low-power continuous sensory processing in smartphones and other battery-operated devices. He earned his BS in Computer Engineering from Valparaiso University in 1991, his M.S. in Electrical and Computer Engineering from Carnegie Mellon University in 1992, followed by his Ph.D. in 1997. His graduate work was supervised by Prof. John Paul Shen.


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