Reconfigurable Computing has arrived! In the last year, Intel has bought Altera and Microsoft has invested significant resources to bring Field-Programmable Gate Arrays (FPGAs) to the cloud. Reconfigurable computing, in which processors are augmented with a programmable fabric to accelerate certain applications, will be disruptive and is poised to change the computing landscape. Bringing FPGAs to the masses, however, is going to be challenging. We need new design flows, architectures, and entire ecosystems.
In the first part of this course, we will take a step back and look at what we have already accomplished. We will examine several types of flexible hardware fabrics, including FPGAs and coarse-grained architectures. To better appreciate the CAD challenges, we will spend some time talking about the nuts and bolts of FPGA CAD. We will also talk about the integration of processors into an FPGA fabric, ranging from tightly-coupled schemes to more traditional co-processor style architectures.
In the second part of the course, we will look forward. One of the most important challenges is design productivity. Hardware designers might be willing to accept long compile times, thinking in RTL, and dealing with complex debug tools, but if reconfigurable computing is to go mainstream, none of this will be acceptable. We will talk about recent efforts in improving design productivity (including high-level synthesis) and methods for creating a debug and optimization ecosystem that allows software designs to create fast, efficient, and correct designs for FPGAs.
Steve Wilton is a Professor and Associate Head in the Department of Electrical and Computer Engineering at the University of British Columbia.His research focuses on the architectures of next-generation Field-Programmable Gate Arrays and their associated Computer-Aided Design Tools. Along with his students, he has published over 100 papers in many areas related to Field-Programmable Technology, ranging from flexible memories, routing architectures, power-efficient architectures, packing, placement, and routing algorithms, analytical modeling and debugging techniques. He has spent time at Imperial College London and IMEC, and has been a consultant for Altera, Cypress, and Cadence. He was also a co-founder of Veridae Systems (acquired by Tektronix in 2011), which developed debug solutions for ASICs, FPGAs, and FPGA-based systems. He is the Editor-in-Chief of the ACM Transactions on Reconfigurable Technology and Systems. He received best paper awards at the International Symposium on Field-Programmable Custom Computing Machines in 2015, the International Conference on Field-Programmable Technology in 2003, 2005, 2007, and 2013 and at the International Conference on Field-Programmable Logic and Applications in 2001 , 2004, 2007, and 2008.