Slot 3

High-Performance On-Chip Interconnects for Emerging SoCs
Tushar Krishna, Georgia Tech, USA

Abstract

Interconnection Networks refer to the communication fabric interconnecting various components of a computer system. They occur at various scales – from on-chip networks (OCN)/Networks-on-Chip (NoCs) in billion-transistor many-core chips, to custom high-speed wired networks in HPC supercomputers, to optical fiber networks within datacenters. The growing emphasis on parallelism, distributed computing, heterogeneity, and energy-efficiency across all these systems makes the design of the communication fabric critical to both high-performance and low power consumption.
This course examines the architecture, design methodology, and trade-offs of interconnection networks. The material covered in this course bridges the gap between disciplines/courses such as VLSI interconnects, digital communication, computer architecture, distributed systems, and computer networks. The focus of the course will be on on-chip interconnection networks for emerging SoCs that comprise heterogeneous cores and accelerators. The insights and learning will span chip-scale, rack-scale, and datacenter-scale networks as well.

Lectures will cover the fundamental building blocks of interconnection networks, getting to the research frontier at each level – topology, routing, flow-control, microarchitecture, network interfaces, and system interactions. Each class will also provide a short hands-on coding sprint/demo of the topic discussed using the Garnet2.0 network-on-chip simulator, along with snippets of RTL. By the end of the course, students will acquire the intuition and skill-set required to build and evaluate a state-of-the-art network-on-chip that meets desired performance, area, and energy specs for the target system (homogeneous many-core, heterogeneous SoC, or a spatial accelerator).

Bio

Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech, with an adjunct appointment in the School of Computer Science. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2014. Prior to that he received a M.S.E in Electrical Engineering from Princeton University in 2009, and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi in 2007. Before joining Georgia Tech in 2015, Dr. Krishna worked as a researcher in the VSSAD Group at Intel, Massachusetts for 14 months, designing spatial accelerator architectures and HPC networks.

Dr. Krishna's research spans the computing stack: from circuits/physical design to microarchitecture to system software. His key focus has been in architecting the communication networks and protocols between homogeneous/heterogeneous/reconfigurable computer systems, both on-chip and off-chip. He has over two dozen publications in leading computer architecture and EDA conferences and journals and holds one patent. Two of his papers have been selected in IEEE Micro’s Top Picks from Computer Architecture, and two have won best paper awards. He has also served on the Program Committees of MICRO, DAC, DATE, and Hot Interconnects.

Dr. Krishna is a co-author of the book “On Chip Networks, 2nd Edition”, which is part of the Synthesis Lectures on Computer Architecture. Morgan & Claypool Publishers. 2017. He is also the developer of the Garnet2.0 network-on-chip simulator which is part of the gem5 (www.gem5.org) full-system simulator, one of the most widely used open-source computer architecture simulators across academia and industry.


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