Slot 2

Memory Technology and Architecture
Thomas Pawlovski, Micron Technology, Inc.

Abstract

Memory is an essential part of any computing system. The ideal memory is cheap, large, fast and parallel. Unfortunately, such a memory does not exist, and instead there is a myriad of technologies and architectures to optimize memory performance at an affordable cost. This course will cover the following topics:

- A history of memory technologies and architectures
- The technology, scaling outlook, characteristics, and operation of the major memory types: SRAM, DRAM, NOR FLASH, NAND FLASH, 3D memory, emerging memories
- Classic memory hierarchy pyramid
- How hosts see memory
- Memory interfaces
- Attachment and control of memories to processor systems (e.g. in DRAM scheduling accounting for rows, pages, banks, ranks, policies)
- Performance modelling
- Error management
- Processing in Memory, Processing Near Memory

Bio

J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Advanced Computing Solutions Group. His responsibilities include advising on new technologies, investments, system architectures and memory product/subsystem architectures.

For the past twenty-six years at Micron Mr. Pawlowski has had the pleasure of making key technical contributions to many new memory and system architectures such as synchronous burst pipelined SRAM; ZBT SRAM; DDR and QDR SRAM, PSRAM; high-speed NAND; multi-channel memory; DDR DRAM; RLDRAM; 3D memory; LPDRAM, HBM, Micron Automata Processor; abstraction protocols; new ECC concepts; processing near memory concepts and others yet to be announced. His current projects include 3DXpoint system architecture, emerging memory architectures, and further advances in future high-performance DRAM. Mr. Pawlowski serves on numerous conference committees and advisory boards. He has been a keynote speaker at many conferences such as MemSys, MICRO, IPDPS and others. He has served as chair of several JEDEC committees including SRAM, Flash, and was the founding father and chair of the low power memory committee for DRAM and Flash.

Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada and has over 150 U.S. patents granted and in- progress. He was named an IEEE Fellow for his contributions to memory.


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