The historical evolution of supercomputing technologies and of embedded computing technologies exhibits a convergence of targets that narrows the gap tween such traditionally distant worlds, and paves the way to an extraordinary future societal scenario. As a consequence, the sovereignty on power-efficient high-performance microprocessor technology has become a transversal strategic capability for the advancement of modern nations. Europe, after years of delay with respect to other advanced regions of the world, has now started a set of initiatives to gain a new leading position in computing technology. The first large investment in such direction is represented by the European Processor Initiative, a 4-year 26-partner project whose aim is to design and implement a roadmap for a new family of low-power European processors, for extreme scale computing and a range of emerging applications. The initial core drivers of the development are supercomputing, AI for Big Data, and future Automotive systems. The opening keynote talk of the HiPEAC ACACES School 2019 will address the motivation, objectives, timeline, and technical insights of this unprecedented project, also highlighting the opportunities for further developments.
Mauro Olivieri received the Master (Laurea) degree in electronics engineering and the Doctorate degree in electronics and computer engineering from the University of Genoa, Italy, where he was an assistant professor from 1995 to 1998. In 1998 he joined Sapienza University of Rome as an associate professor, teaching Digital Electronics and Digital Integrated System Architectures. His research interests are digital system-on-chip design, microprocessor core design, and digital nano-scale circuits. He was the scientific responsible for Sapienza University for 2 FP7 ENIAC JU European projects, 1 FP7 IAPP European project, 4 PRIN/FIRB national projects, 11 MIUR University Projects, and 8 industrial research contracts. He was a technical expert for the Italian Economic Development Ministry in the “Smart Specialization Strategy” project on the topic “Smart Cities/Communities”. He is an evaluator for the European Commission in the ECSEL Joint Undertaking. He is a visiting researcher at the Barcelona Supercomputing Center, Spain, within the European Processor Initiative project. He authored over 110 papers and a textbook in three volumes on digital VLSI design. He has been a TPC member of IEEE DATE and was General Co-Chair of IEEE/ACM ISLPED’15. He is a senior member of the IEEE.
All startups are different, and there is no magic sauce or formula that will guarantee success. Running a traditional startup is also VERY different from running a successful research project. There are, of course, new areas to understand, such as law, taxes, financing, investors, IP, business planning, validation, prototyping, production, marketing and sales. But not even the most basic areas of the research, such as the baseline systems, simulation methodologies and evaluation principles, may hold for a startup. The most brilliant research ideas can lead to an unsuccessful startup if all areas are not understood and dealt with appropriately. I will share my experience from running two startups: one a more traditional startup that attempted to cover all the areas, and the other a scaled-down attempt to avoid most of the areas.
Erik Hagersten has moved between industry and academia about ten times. He holds a professor chair in computer architecture at Uppsala University in Sweden since 1999. Prior to this, he was the chief architect for Sun Microsystem's high-end server engineering division in the US 1994-1999. In 2006 he founded Acumem AB, developing new modeling technology for multicore software optimisations. Acumem was acquired by Rogue Wave Software Inc. in 2010. In 2014 he founded Green Cache AB, developing new and efficient tag-less cache architectures. Green Cache was sold in 2018.
At Uppsala, Erik has built up he Uppsala Architecture Research Team, UART (it.uu.se/research/group/uart) – one of the largest architecture research groups in Europe. UART performs research in fast performance modelling technology, compiler technology as well as more traditional computer architecture topics. He is a member of the Royal Swedish Academy of Engineering Sciences (IVA) since 2002.
The topics of this year's Summer School will be presented by the following world-class experts:
The structure of the Summer School is such that the participants will have the opportunity to intensely interact with the lecturers during the full duration of the summer school (during meals, breaks, evening activities). All lecturers will stay on campus during the full week.
The summer school consists of 12 courses spread over two morning slots and two afternoon slots. Per slot there are three parallel courses of which you can take only one. When applying for admission, you will be asked to indicate your preference.
The courses have been allocated to slots in such a way that it is in any case possible to create a summer school program that matches your research interests.