Slot 1

Working with RISC-V: from open ISA to open Architecture to open Hardware
Luca Benini and Frank Gurkaynak, ETH Zürich, Switzerland

Abstract

In this course, we will provide an in-depth discussion on RISC-V processors, starting from ISA organization, moving to micro-architecture and finally to design and implementation. We will focus on the distinctive advantages offered by RISC-V openness and extensibility across these abstraction layers. We will use the open RISC-V cores from the PULP platform (the Zero-riscy aka IBEX tiny core, the Riscy aka CORE-V-CV32E with FP and XPULP extensions, the ARIANE 64-bit application processor and the ARA double-precision FP vector processor) as concrete case studies. We will also discuss opportunities and challenges related to the silicon implementation of these RISC-V cores in academic and commercial Systems-on-Chip and share our experience and vision for the future on open cores and open hardware for research and business.

Bio

Luca Benini holds the chair of digital Circuits and systems at ETHZ, and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. He served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He has published more than 1000 peer-reviewed papers and five books. He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg Award and 2019 IEEE TCAD Donald O. Pederson Best Paper Award.

Frank K. Gürkaynak is a senior scientist at ETH Zürich working in the Digital Circuits and Systems group, as well as the director of Microelectronics Center, which supports IC Design, FPGA and PCB design efforts within ETH Zürich. His research interests include low power computer architectures, cryptographic hardware, testing of digital circuits and asynchronous circuits. Frank was involved with the PULP project since its beginning in 2013. He has been involved in teaching topics for IC Design for almost 25 years at ETH Zurich, EPFL, Worcester Polytechnic Institute and Istanbul Technical University.


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